1. Field of the Invention
This invention relates generally to electronic driver circuits, and more particularly to a novel system and method for reducing inter-pixel electrical fields in a flat panel display.
2. Description of the Background Art
FIG. 1 shows a single pixel cell 100 of a typical liquid crystal display. Pixel cell 100 includes a liquid crystal layer 102, contained between a transparent common electrode 104 and a pixel storage electrode 106, and a storage element 108. Storage element 108 includes complementary data input terminals 110 and 112, data output terminal 114, and a control terminal 116. Responsive to a write signal on control terminal 116, storage element 108 reads complementary data signals asserted on a pair of bit lines (B+ and B-) 118 and 120, and latches the signal on output terminal 114 and coupled pixel electrode 106.
Liquid crystal layer 102 rotates the polarization of light passing through it, the degree of rotation depending on the root-mean-square (RMS) voltage across liquid crystal layer 102. The ability to rotate the polarization is exploited to modulate the intensity of reflected light as follows. An incident light beam 122 is polarized by polarizer 124. The polarized beam then passes through liquid crystal layer 102, is reflected off of pixel electrode 106, and passes again through liquid crystal layer 102. During this double pass through liquid crystal layer 102, the beam's polarization is rotated by an amount which depends on the data signal being asserted on pixel storage electrode 106. The beam then passes through polarizer 126, which passes only that portion of the beam having a specified polarity. Thus, the intensity of the reflected beam passing through polarizer 126 depends on the amount of polarization rotation induced by liquid crystal layer 102, which in turn depends on the data signal being asserted on pixel storage electrode 106.
Storage element 108 can be either an analog storage element (e.g. capacitative) or a digital storage element (e.g., SRAM latch). In the case of a digital storage element, a common way to drive pixel storage electrode 106 is via pulse-width-modulation (PWM). In PWM, different gray scale levels are represented by multi-bit words (i.e., binary numbers). The multi-bit words are converted to a series of pulses, whose time-averaged root-mean-square (RMS) voltage corresponds to the analog voltage necessary to attain the desired gray scale value.
For example, in a 4-bit PWM scheme, the frame time (time in which a gray scale value is written to every pixel) is divided into 15 time intervals. During each interval, a signal (high, e.g., 5V or low, e.g., 0V) is asserted on the pixel storage electrode 106. There are, therefore, 16 (0-15) different gray scale values possible, depending on the number of "high" pulses asserted during the frame time. The assertion of 0 high pulses corresponds to a gray scale value of 0 (RMS 0V), whereas the assertion of 15 high pulses corresponds to a gray scale value of 15 (RMS 5V). Intermediate numbers of high pulses correspond to intermediate gray scale levels.
FIG. 2 shows a series of pulses corresponding to the 4-bit gray scale value (1010), where the most significant bit is the far left bit. In this example of binary-weighted pulse-width modulation, the pulses are grouped to correspond to the bits of the binary gray scale value. Specifically, the first group B3 includes 8 intervals (2.sup.3), and corresponds to the most significant bit of the value (1010). Similarly, group B2 includes 4 intervals (2.sup.2) corresponding to the next most significant bit, group B1 includes 2 intervals (2.sup.1) corresponding to the next most significant bit, and group B0 includes 1 interval (2.sup.0) corresponding to the least significant bit. This grouping reduces the number of pulses required from 15 to 4, one for each bit of the binary gray scale value, with the width of each pulse corresponding to the significance of its associated bit. Thus, for the value (1010), the first pulse B3 (8 intervals wide) is high, the second pulse B2 (4 intervals wide) is low), the third pulse B1 (2 intervals wide) is high, and the last pulse B0 (1 interval wide) is low. This series of pulses results in an RMS voltage that is approximately .sqroot.2/3 (10 of 15 intervals) of the full value (5V), or approximately 4.1 V.
FIG. 3 shows 3 pixel cells 100(a-c) arranged adjacent one another, as in a typical flat panel display. Problems arise in such displays, because differing signals on adjacent pixel cells can cause visible artifacts in a display image. For example, electrical field lines 302 indicate that logical high signals are being asserted on each of pixel electrodes 106(a and c). The absence of an electrical field across pixel cell 100(b) indicates that a logical low signal is being asserted on pixel electrode 106(b). Note that in addition to the electrical fields 302 across liquid crystal layers 102(a and c), transverse fields 304 exist between pixel electrodes 106(a and c), carrying a logical high signal, and pixel electrode 106(b), carrying a logical low signal. Transverse fields 304 affect the polarization rotation of the light passing through liquid crystal layers 102(a-c), and, therefore, potentially introduce visible artifacts. Whether, and to what extent, visible artifacts are produced between adjacent pixel cells depends on the time period that logically opposite signals (i.e., high and low) are asserted on adjacent pixel electrodes. Adjacent pixel cells carrying opposite signals are said to be out of phase.
The transverse electrical field problem is particularly noticeable in systems which drive a display with binary weighted pulse width modulation data. In such systems, because the least-significant-bit (LSB) time is too short to allow a driver circuit to write to all of the rows of a display, the rows of the display must be grouped in segments, and the LSBs must be written to the rows of the individual segments at different times. Examples of such schemes include writing the LSBs in or between more significant bits, offsetting the LSBs with respect to each other, and writing segments "off" to provide the additional time required to write the remaining LSBs to the display. Each of these schemes, however, substantially increases the potential for the occurrence of visible artifacts along the boundaries between adjacent display segments.
FIG. 4 is a timing diagram 400 illustrating the case where an LSB (i.e., B0) is written between two more significant bits (i.e., B5 and B4). The vertical axis 402 in timing diagram 400 corresponds to the physical positions of two adjacent segments (groups of rows) X 404 and Y 406 within a display. Segment X 404 and segment Y 406 each contain a group of display rows, and are separated by an intersegment boundary 408 disposed between a bottom row of segment X 404 and a top row of segment Y 406.
The horizontal position in diagram 400 corresponds to the progression of time. At some time prior to the time period displayed by timing diagram 400, bit B5 was written to segments X 404 and Y 406. Then, at a time t.sub.0, the least significant bits (B0) of data are written to the pixels of a first row (not shown) of segment X 404, and continue to be sequentially written to subsequent rows of segment X 404 until, at a time t.sub.1, each pixel of each row of segment X 404 contains bit B0 of the data intended for each respective pixel. Next, from a time t.sub.2 to a time t.sub.3, bit B4 is written to segment X 404, replacing bit B0, and immediately thereafter, from time t.sub.3 to time t.sub.4, bit B0 is written to segment Y 406, replacing bit B5. Next, from a time t.sub.5 to a time t.sub.6, bit B4 is written to segment Y 406, replacing bit B0.
Note that from time t.sub.1 to time t.sub.3, and again from time t.sub.3 to time t.sub.5 different bits are being asserted on the pixels of the rows on either side of intersegment boundary 408. In particular, from time t.sub.1 to time t.sub.2, B0 is being asserted on the last row of segment X 404 and B5 is being asserted on the first row of segment Y 406. Additionally, from time t.sub.3 to time t.sub.5, B4 is being asserted on the last row of segment X 404 and B0 is being asserted on the first row of segment Y 406. When the data bits being asserted on opposite sides of intersegment boundary 408 have different values (i.e., one is high and the other is low), a transverse electrical field is created across intersegment boundary 408. The transverse field is intensified when the image displayed at intersegment boundary 408 is of uniform intensity, because it is then highly probable that all of the pixels in the rows on either side of intersegment boundary 406 will be displaying the same value (i.e. all B5s will have the same value, all B4s will have the same value, and all B0s will have the same value). In such cases, the transverse field across intersegment boundary 408 causes an unacceptable visible horizontal line across the displayed image.
What is needed is a system and method for reducing the transverse electrical fields across the intersegment boundaries of displays to eliminate the visible artifacts caused thereby.